Schottky-Embedded Isolation Ring to Improve Latch-Up Immunity Between HV and LV Circuits in a 0.18 μm BCD Technology

As the high-voltage (HV) and low-voltage (LV) circuits are integrated together in a common silicon substrate, parasitic latch-up path between neighboring HV LV with limited spacing layout would be triggered into state to cause unrecoverable failure chip. In this work, isolation ring of n-well (HVNW) / N-buried layer (NBL) Schottky-embedded junction overcome lateral HV-to-LV was proposed verified $0.18{\mu }\text{m}$ bipolar-CMOS-DMOS (BCD) technology. From experiment results ring, holding voltage (Vh) can increased greater than difference different power supplies circuits. Furthermore, significantly reduced save chip area. The is cost-effective solution provide good immunity among circuit blocks short distance.